1. Field of the Invention
The present invention relates generally to flash memory devices. More particularly, the invention relates to a flash memory device capable of preventing the so-called erase disturb phenomenon.
2. Description of the Related Art
Non-volatile memory devices retain stored data even when applied power is interrupted. Flash memory is one form of commonly available non-volatile memory. The block memory erase function provided by flash memory makes it ideal for incorporation into computers, memory cards, consumer electronics, etc.
Conventional flash memory is provided in two principal types; NOR-type and NAND-type, depending on the connection patterns between constituent memory cells and bitlines. NOR-type flash memory is more difficult to densely integrate, but supports relatively higher speed operations. NAND-type flash memory is capable of denser integrated because it generally uses less electrical current during operation of its memory cells.
NAND flash memory includes a memory cell array as a data storage medium. The memory cell array includes a plurality of blocks each comprising a plurality of cell strings (or NAND strings). A typical flash memory cell is implemented on a P-type semiconductor substrate, using N-type source/drain regions separated by a channel region, a floating gate storing charge, and a control gate disposed above the floating gate.
A page buffer circuit is provided in the flash memory to store write data ultimately written to the memory cell array or read data retrieved from the memory cell array. As is well understood in the art, the memory cell of a NAND-type flash memory is erased and programmed using the Folwer-Nordheim tunneling (or “FN tunneling”) effect. Typical programming and erase operations associated with contemporary NAND-type flash memory are disclosed, for example, in U.S. Pat. Nos. 5,473,563 and 5,696,717, the collective subject matter of which is hereby incorporated by reference.
Generally speaking, the storing of data in a flash memory cell includes the steps of first erasing the flash memory cell and then programming the erased cell. The erase operation is performed on a memory cell (or a group of memory cells) by applying an erase voltage (e.g., 0V) to the control gate and applying a high voltage (e.g., 20V) to the semiconductor substrate. Under the above voltage condition, FN tunneling occurs to force electrical charge accumulated on the floating gate to the substrate through a tunneling oxide layer separating the floating gate from the substrate.
A typical stack-type flash memory device (hereinafter referred to as “stack flash memory”) includes a plurality of memory cell arrays. The stack flash memory includes a layer decoder and a row decoder. The layer decoder selects any memory cell array in response to a received layer address, and the row decoder selects any memory block of the selected memory cell array in response to a received row address.
The row decoder includes select transistors respectively associated with individual wordlines. The control gates of the select transistors respectively corresponding to wordlines of a selected memory block are turned ON when an operation power VDD is applied.
During an erase operation, an erase voltage is applied to wordlines of the selected memory block through the “ON” select transistors. Gates of select transistors respectively corresponding to an unselected memory block of a selected memory cell array and wordlines of an unselected memory cell array remain OFF as they receive a ground voltage VSS. Thus, the unselected memory block of the selected memory cell array and the wordlines of the unselected memory cell array enter a floating state.
Since a substrate voltage is applied to a substrate of a memory cell array during the erase operation, floating wordlines of the unselected memory cell array are each boosted to the substrate voltage. Also the wordlines of the unselected memory blocks of the selected memory cell array are each boosted to the substrate voltage. In this case, a voltage difference between the substrate voltage and a wordline is so small that FN tunneling does not occur. As a result, the erase operation is not performed for memory cells of the unselected memory cell array, and memory cells of the unselected memory blocks of the selected memory cell array.
Generally, a ground voltage is applied to sources of select transistors respectively corresponding to wordlines of an unselected memory cell array during an erase operation. A typical select transistor is a transistor through which sub-threshold leakage current (hereinafter referred to as “leakage current”, or Isub) flows. The leakage current flowing through the select transistor is proportional to an exponential function eVgs of a gate-source voltage difference of the select transistor. The voltage of wordlines of an unselected memory cell array may drop due to the leakage current through the select transistor. In this case, unselected cells may be erased. This result is referred to as the “erase disturb”. An erase voltage is applied to unselected memory blocks of a selected memory cell array, but is not applied to the select transistors because they remain in an OFF state. However, since an erase voltage is applied to sources of the select transistors, memory cells of the unselected memory blocks of the selected memory cell array may also suffer from erase disturb when the erase voltage is a ground voltage.